Short channel effects in MOS transistors become increasingly prevalent as device sizes diminish. A consequence of shrinking channel lengths to accommodate denser device packing is "punchthrough", a condition wherein the depletion region from the biased drain region touches the depletion region of the source, resulting in a shorted transistor. Frequently, the punchthrough occurs at a substantial distance below the surface of the device.
One proposal for overcoming punchthrouh is described and claimed in U.S. Pat. No. 4,455,740, issued June 26, 1984 to Hiroshi Iwai. This patent describes a "trench" gate structure, in which the gate is recessed into the substrate surface. A substantial portion of the channel of the transistor appears to extend in a vertical direction. A consequence of the trench gate structure is supposed to be that the channel of the device can be maintained with a dimension long enough to avoid punchthrough but the surface dimension of the channel (i.e. the length of the channel that extends laterally along the substrate surface) is reduced substantially, thus reducing the chip area occupied by the channel. The trench can be made deep enough to form a barrier between the source and drain and prevent source drain punchthrough. However, the approach described by Iwai does not work unless the trench is made inordinately long to prevent the transistor from turning on at the surface. When the transistor turns on at the surface, the device is susceptible to punchthrough around the gate and the beneficial effects described by Iwai cannot be realized. The structures described herein can realize punchthrough immunity, and are operative and practical devices that have significant technological implications. For example, in practice situations will frequently arise wherein if the trench is made deep enough to prevent punchthrough the channel will be unacceptably long. The choice of design length for the channel varies within a relatively narrow margin since the length determines the operating speed of the transistor. Known approaches for overcoming punchthrough effects are to reduce the operating voltage, which results in smaller depletion regions, or to increase the impurity level of the substrate which has the same result. In either case the tendency for source-drain overlap is diminished. However, reducing the drain voltage level has other adverse consequences and increasing the substrate doping leads to increased subthreshold leakage.
Another method for eliminating punchthrough effects, which is not well known, is to place an impurity region selectively between the source-drain regions. That impurity region must lie deep within the substrate so as not to prevent normal operation through the channel of the device. While this approach should prove effective, it is difficult to make with very small dimensions, i.e. in VLSI technology. A major reason for that is that there is no stage in the conventional processing that affords a mask that is convenient or self-aligned to the region in which the implant is to be placed.